The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as few components as possible, thus cutting down the size and the production cost.An SDR solution means that the sampling of the signal is done as close to the antenna as possible. The wide bandwidth needed in such a product is achieved by using SP Devices algorithm for time-interleaved ADCs. Two hardware prototypes and two versions of the software were designed and implemented using this technology.They were also analyzed within this thesis work. The results proved to be good, and the possibilities to produce a commercial software-defined radio receiver for the VHF-band are good.
Contents
1 Introduction
1.1 Background
1.2 Purpose and Method
1.3 Prerequisites
1.4 Tools
1.4.1 Protel
1.4.2 Matlaband Simulink
1.4.3 Xilinx ISE
1.4.4 Microsoft Visual Studio
1.5 Restrictions
1.6 Report Disposition
1.7 Reading Instructions
2Linearizer
2.1 Problems with Interleaved ADCs
2.1.1 GainMismatch
2.1.2 OffsetError
2.1.3 Time-Skew
2.2 TheSolution
3 Superheterodyne vs SDR
3.1 Introduction
3.2 Traditional Superheterodyne RF Receiver
3.2.1 Advantages
3.2.2 Disadvantages
3.3 Software-Defined Radio Receiver
3.3.1 Advantages
3.3.2 Disadvantages
4 Basic RF Receiver Concepts
4.1 Signal-to-Noise Ratio
4.2 Receiver Noise
4.3 Intermodulation Distortion & Intercept Point
4.4 Dynamic Range
4.5 Spurious-Free Dynamic Range
4.6 Effective Number of Bits
4.7 Oversampling in Analog-to-Digital Converters
5Requirements
5.1 Bandwidth
5.2 Sensitivity
5.3 Intermodulation Response Rejection and Blocking
5.4 Adjacent Channel Selectivity
5.5 Signal-to-Noise Ratio
6 Analog Front-End
6.1 Front-End Architecture
6.2 Choise of Components
6.2.1 ADC
6.2.2 LNAandVGA
6.2.3 Analog Filters
6.2.4 FPGA
6.2.5 USB-to-UART Interface
6.2.6 DAC
6.2.7 Crystal Oscillator and Clock Buffer
6.2.8 Linear Voltage Regulators
6.3 Theoretical Calculations
6.3.1 SNR
6.3.2 IMD3
6.4 PCBandEMC[13]
7 Data Packets
7.1 ThePacket
7.1.1 Training Sequence
7.1.2 Start Flag
7.1.3 Data
7.1.4 Frame Check Sequence
7.2 Bit Stuffing
7.3 NRZI
7.4 GMSK
7.4.1 Gaussianfilter
8FPGA
8.1 Hardware Prerequisites
8.1.1 DSP-slices
8.2 First Attempt
8.2.1 Linearizer
8.2.2 First Decimation
8.2.3 I-Q Modulation
8.2.4 Second Decimation
8.2.5 Third Decimation
8.2.6 Phase Differentiator
8.2.7 FIFO
8.2.8 Data Transfer
8.2.9 DAC Controller
8.3 Second attempt
8.3.1 Linearizer
8.3.2 IQ-modulation
8.3.3 Decimation
8.3.4 Phase Differentiator
8.3.5 FIFO
8.3.6 Serial Interface
8.3.7 DAC Controller
8.4 Calculations
8.4.1 Scaling
8.4.2 Word Length
9PC
9.1 Communication
9.2 Matlab
9.2.1 Symbol Synchronization
9.2.2 Decode NRZI
9.2.3 Extraction of the Data
10 Tests and Results
10.1FilterBandwidths
10.1.1Board1
10.1.2Board2
10.2External LNA
10.3SNR
10.3.1 Variable Gain – Fixed Signal Level
10.3.2 Fixed Gain – Variable Signal Level
10.4Sensitivity Test
10.4.1Board1
10.4.2Board2
10.5BlockingTest
10.6IntermodulationTest
10.7AdjacentChannelSelectivity
10.8 Power Consumption
11 Conclusions and Future Work
11.1Conclusions
11.1.1Test Results
11.1.2Hardware
11.1.3FPGA
11.2FutureWork
References
Author: Athari, Emad,Lerenius, Petter
Source: Linköping University
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