Baseband processing and baseband processors will become increasingly important in the future when more and more devices will be connected together by means of wireless or wire-line links. Since the number of radio standards grows increasingly fast and the diversity among the standards increases, there is a need for a processing solution capable of handling as many standards as possible and at the same time not consuming more chip area and power than a single-standard product.
In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named “Single Instruction stream Multiple Tasks”, SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor…
Contents
1 Introduction
1.1 Scope of the dissertation
1.2 Organization
2 System environment
2.1 Introduction
2.2 Baseband processing tasks
3 Motivation
3.1 Introduction
3.2 Software Defined Radio
3.3 Technical aspects
3.3.1 Hardware and software reuse
3.3.2 Dynamic resource allocation
3.4 Market aspects
3.4.1 Implementation flexibility
3.5 Military SDR – JTRS
3.6 Bridging the computing complexity gap
3.7 Summary of challenges
3.8 References
4 Research methodology
II Programmable baseband processors
5 Baseband signal processing
5.1 Introduction
5.2 Challenges
5.2.1 Multi-path propagation and fading
5.2.2 Dynamic range
5.2.3 Mobility
5.2.4 Radio impairments
5.2.5 Processing capacity challenges
5.3 Modulation methods
5.3.1 Single Carrier
5.3.2 OFDM
5.3.3 CDMA
5.4 Baseband processing properties
5.4.1 Complex computing
5.4.2 Vector property and control flow
5.5 References
6 Acceleration
6.1 Introduction
6.1.1 Function level acceleration
6.1.2 Instruction level acceleration
6.2 Accelerator selection method
6.3 Configurability and flexibility
6.4 Accelerator integration
6.5 Case study: Acceleration in multi-standard modems
6.5.1 Introduction
6.5.2 Analysis
6.5.3 Radio front-end processing
6.5.4 Symbol processing
6.5.5 Demappimg
6.5.6 Forward error correction and channel coding
6.5.7 Results
6.6 References
7 Related work
7.1 Introduction
7.2 Traditional implementations
7.3 Silicon Hive – Avispa-CH1
7.4 Hipersonic-1, OnDSP and EVP16
7.5 Icera – DXP
7.6 Sandbridge Technology – Sandblaster
7.7 TU Dresden – SAMIRA
7.8 Morpho Technologies – MS2
7.9 FPGA and ASIC technology
7.10 Discussion
7.10.1 Vector instructions
7.10.2 Cache memories
7.10.3 Acceleration
7.11 Concluding remarks
7.12 References
III SIMT baseband processors
8 The SIMT Architecture
8.1 Introduction
8.2 Assembly Instruction Set
8.3 Single Issue Multiple Tasks
8.4 SIMD execution units
8.4.1 Vector management
8.4.2 Complex MAC SIMD unit
8.4.3 Complex ALU SIMD unit
8.5 On-chip network
8.5.1 Complex network
8.5.2 Integer network
8.6 Controller core
8.6.1 Multi context support
8.7 Memory system
8.7.1 Addressing
8.8 Accelerator integration
8.9 References
9 SIMT Design flow
9.1 Introduction
9.2 Design methodology
9.2.1 Analysis of the covered standards
9.2.2 Algorithm selection
9.2.3 Mapping and benchmarking
9.2.4 Component selection
9.2.5 Instruction set specification
9.3 Evaluation
9.4 Multi-mode systems
9.5 Case study: Rake receiver
9.5.1 Introduction
9.5.2 Rake based channel equalization
9.5.3 Review of processing challenges
9.5.4 Function mapping
9.5.5 Results and conclusion
9.6 Case study: Memory efficiency in multi-mode OFDM sys-tems
9.6.1 Introduction
9.6.2 Application analysis andmapping to the SIMT archi-tecture
9.6.3 Vector execution units
9.6.4 Memory banks
9.6.5 Results and conclusion
9.7 References
10 Simultaneousmulti-standard execution
10.1 Introduction
10.2 Hardware implications
10.3 Scheduling and task analysis
10.3.1 Task analysis
10.3.2 Context management
10.3.3 Lightweight scheduler
10.4 Case study: UMA
10.4.1 Introduction
10.4.2 Profiling and mapping
10.4.3 Scheduling
10.4.4 Results
10.4.5 Conclusion
10.5 References
11 Low power design
11.1 Introduction
11.2 Low power design
11.2.1 Memory efficiency
11.2.2 Hardwaremultiplexing
11.2.3 Data precision optimization
11.2.4 Low leakage standard cells
11.3 Dynamic power saving
11.3.1 Dynamic data width
11.3.2 Clock gating
11.3.3 Power gating
11.3.4 Integration in the SIMT architecture
11.4 References
12 Software development
12.1 Introduction
12.2 Software development methodology
12.3 Software development
12.3.1 Algorithm selection
12.3.2 Profiling and benchmarking
12.3.3 Hardware dependent behavior modeling
12.3.4 Scheduling
12.3.5 Simulator and Assembler
12.3.6 C-compiler
12.3.7 Ideal tool suite
12.4 References
13 The BBP2 processor
13.1 Introduction
13.2 Architecture
13.2.1 Instruction set
13.2.2 On-chip network
13.2.3 Execution units
13.2.4 Accelerators
13.3 Kernel benchmarking
13.4 Implementation
13.4.1 Cell area of individual components
13.4.2 Clock and power gating
13.5 System demonstrator
13.6 Measurement results
13.7 Scaling
13.8 References
14 Verification and Emulation
14.1 Introduction
14.2 Tool-chain for verification
14.3 Verification methodology
14.3.1 Formal verification
14.4 Lab installation
14.5 Emulation
14.6 References
IV Extensions of the SIMT architecture
15 MIMO andMulticore support
15.1 Introduction
15.2 MIMO
15.2.1 Front-end processing
15.2.2 Channel estimation
15.2.3 Matrix inversion
15.2.4 Integration in the SIMT architecture
15.3 Multicore support
15.3.1 Memory management
15.3.2 Integration in the SIMT architecture
15.4 References
V Conclusions and future work
16 Conclusions
16.1 Achievements
16.1.1 Algorithm selection and development
16.1.2 Models
16.1.3 Accelerator selection
16.1.4 Instruction issue
16.1.5 Simultaneous multi-standard execution
16.1.6 SIMT components
16.1.7 System demonstrator
16.2 The SIMT architecture
17 Future work
17.1 Multi-standard FEC processors
17.2 MIMO
17.3 Multi-core systems
17.3.1 Wireless base-stations
17.3.2 Radar systems
17.4 Concluding remarks
Author: Nilsson, Anders
Source: Linköping University
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