There is a lot of applications for DSPs (Digital Signal Processor) in the most rapidly growing areas in the industry right now as wireless communication along with audio and video products are getting more and more popular. In this report, a DSP, developed at the division of Computer Engineering at the University of Linköping, is optimized and verified.Register Forwarding was implemented on a general architecture level to avoiddata hazards that may arise when implementing instruction pipelining in a processor.The very common FFT algorithm is also optimized but on instruction setlevel. That means the algorithm is carefully analyzed to find operations that mayexecute in parallel and then create new instructions for these parallel operations…
Contents
1 Introduction
1.1 Purpose
1.2 Method
1.3 Thesis Outline
1.4 Notations
1.5 Abbreviations
1.6 Glossary
2 Background
2.1 Important Properties of Two’s Complement
2.1.1 Subtraction
2.1.2 Rounding
2.1.3 Saturation
2.2 Instruction Pipelining
2.2.1 Data Hazards
2.2.2 Branch Hazards
2.2.3 Structural Hazards
3 The Senior DSP
3.1 Pipeline Architecture
3.2 Module Description
3.2.1 Register File
3.2.2 Special Purpose Register
3.2.3 ALU
3.2.4 MAC
3.2.5 PC Controller
3.2.6 Instruction Decoder
3.2.7 Address Generation Unit
3.3 Software Tool Chain
3.3.1 Assembler
3.3.2 Simulator
4 Register Forwarding
4.1 Initial Architecture
4.2 Implementation
4.2.1 Common Forwarding Point
4.2.2 Forwarding Data
4.2.3 Resolving Structural Hazards
5 Stack
5.1 Implementation
5.1.1 Stack Operating Instructions
5.1.2 Subroutine Calls
5.1.3 Interrupts
6 FFT Acceleration
6.1 Butterfly Operation
6.2 Bit Reverse Addressing
6.2.1 Implementation
6.3 Proof of Concept
6.3.1 Finite Word-length Details
6.3.2 Input Data and Scaling
6.3.3 Result
6.3.4 Performance
7 I/O and Peripherals
7.1 Interface and Structure
7.1.1 General I/O
7.1.2 The Core
7.1.3 Peripherals
7.1.4 Accelerators
7.2 The Simulator
7.3 The Assembler
7.4 Peripheral Modules
7.4.1 Timer
7.4.2 Multiplier
8 Verification
8.1 Instruction Set Corners
8.1.1 About Corner Cases
8.1.2 The Corner Case Suite
8.1.3 Data Corner Combination Test
8.2 Random Instruction Generator
9 Discussion
9.1 Register Forwarding
9.2 Stack
9.3 FFT Acceleration
9.4 The I/O and Peripheral Interface
9.5 The Test Suite
9.6 Future Work
Bibliography
Author: Svensson, Markus,Österholm, Thomas
Source: Linköping University
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