The semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). In order to handle design complexity and to meet short time-to-market requirements, it is increasingly common to make use of a modular design approach where an SOC is composed of pre-designed and pre-verified blocks of logic, called cores…
Contents
1. Introduction
1.1. Introduction and Motivation
1.2. Contributions
1.3. Thesis Organization
2. Background
2.1. IC Design and Fabrication Process
2.2. Core-Based SOC Design Flow
2.3. Test Process
2.4. Core-based SOC Test
2.5. Optimization Techniques
3. Related Work
3.1. Test-Architecture Design
3.2. Test Scheduling
3.3. Test-Data Compression
3.4. Test Sharing and Broadcasting
3.5. Test-Architecture Design and Test Scheduling
3.6. Test-Architecture Design with Compression
3.7. Test-Architecture Design and Test Scheduling with Compression
3.8. Test-Architecture Design and Test Scheduling with Compression and Sharing
3.9. Summary
4. Preliminaries
4.1. System Model
4.2. Test-Architecture Design
4.3. Test Scheduling
5. Test-Architecture Design and Scheduling with Sharing
5.1. Introduction
5.2. Test-Architecture
5.3. The Test Sharing Problem
5.4. The Proposed Sharing Function
5.5. Analysis of Test Sharing
5.6. Broadcasting of a Shared Test
5.7. Motivational Example
5.8. Problem Formulation
5.9. Constraint Logic Programming Modelling
5.10. Experimental Results
5.11. Conclusions
6. Test-Architecture Design and Scheduling with Compression and Sharing
6.1. Introduction
6.2. Test-Architecture
6.3. Test-Data Compression and Sharing
6.4. Test-Architecture Design and Test Scheduling
6.5. Problem Formulation
6.6. Proposed Algorithm
6.7. Experimental Results
6.8. Conclusions
7. Compression Driven Test-Architecture Design and Scheduling
7.1. Introduction
7.2. Test-Architecture
7.3. Analysis of Test-Data Compression
7.4. Problem Formulation
7.5. Proposed Algorithm
7.6. Lower Bound on Test Application Time
7.7. Experimental Results
7.8. Conclusions
8. Test-Architecture Design and Scheduling with Compression Technique Selection
8.1. Introduction
8.2. Test-Architecture
8.3. Analysis of Test-Data Compression
8.4. Problem Formulation
8.5. Proposed Algorithm
8.6. Experimental Results
8.7. Conclusions
9. Test Hardware Minimization…..
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Author: Larsson, Anders
Source: Linköping University
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Keywords: projects, dissertation, thesis, project report