The U.S Global Positioning System (GPS) is a satellite based navigation system that provides worldwide coverage. Typical use of the system includes positioning and timing. However, it can be used for other applications such as GPS bistatic radar, which in turn can be used for altimetry by calculating the delay between the direct and the reflected signal. It can also be used as a passive system (no user transmitted Radio Frequency, RF, energy) for remote sensing. The basic principle for GPS bistatic radar is that by using two receivers, one for direct and one for ground reflected GPS signals, differential processing can be performed to extract more information than just the position. By analysing the shape and the relative power of the reflected signal, information about the reflection surface can be acquired.
To perform this kind of science with GPS, normal receivers can not be used since they lack the flexibility and low-level output that is critical for this kind of processing. The receiver for the reflected signal requires many correlators, in order to see a wide time window, while a typical GPS receiver only has two correlators per channel. Having multiple correlators also gives other advantages, with a narrow spacing there is less tracking jitter and better correlation peak resolution. A larger number of Automatic Gain Control (AGC) bits, 4 or more, than what is typically used for position, one or two, is also good in order to increase resolution.
If a sampling receiver is used, in other words a receiver that outputs Intermediate Frequency (IF) samples, very large data files are created during each experiment. Processing these files in software can be very time-consuming so there is a need for hardware acceleration. To implement a large number of correlators for an experimental real-time receiver or processing module there is only one option and that is Field Programmable Gate Array (FPGA) design. This design is based on the Wildcard II from Annapolis Microsystems, it is a PCMCIA card with a FPGA that connects to the PCI bus of the host computer and thus allows for communication between host and logic.
The design is of a parallel nature and therefore provides a significant increase in performance compared to software processing.
Author: Junered, Marcus
Source: Lulea University of Technology
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