The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc. These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates. One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes…
Contents
I Background
1 Introduction
1.1 Background
1.2 Scope of the Thesis
1.3 Contributions
1.4 Organization of the Thesis
2 Multi-standard Radio Systems and Software Defined Radio
2.1 Trends in Wireless Systems and Devices
2.2 Software Defined Radio
2.3 JTRS and SCA
Bibliography
II Design of Programmable Baseband Processors
3 Application Specific Processors
3.1 Introduction
3.2 Acceleration Techniques
3.2.1 Instruction Level Acceleration
3.2.2 Special Addressing
3.2.3 Function Level Acceleration
3.3 Design Flow
3.3.1 Requirement Specification
3.3.2 Behavior Modeling
3.3.3 Initial Architecture Plan and MIPS Estimation
3.3.4 Instruction Set Design and Architecture Planning
3.3.5 Instruction Set Simulator
3.3.6 Benchmarking and Profiling
3.3.7 Acceleration
3.3.8 Architecture Design
3.3.9 RTL Implementation and Backend Flow
3.3.10 Verification
3.3.11 Concluding Remarks
3.4 Processor Tool Chain
3.5 Low Power Design
3.5.1 Operand Stopping
3.5.2 Memory
3.5.3 Control Overhead
3.5.4 Leakage
3.5.5 Acceleration and Parallelism
3.5.6 DataWidth Masking
Bibliography
4 Introduction to Baseband Processing
4.1 System Overview
4.2 The Transmitter
4.3 The Receiver
4.3.1 Dynamic Range
4.3.2 Synchronization
4.3.3 Channel Estimation and Equalization
4.3.4 Frequency and Timing Offset
4.3.5 Mobility
4.3.6 Demodulation and Channel Decoding
4.4 OFDM Modulation
4.5 Spread Spectrum Modulation
4.6 MIMO Systems
4.7 Computational Complexity
Bibliography
5 Programmable Baseband Processors
5.1 Introduction
5.2 Processing Requirements
5.2.1 Convolution-Based Complex-Valued Processing
5.2.2 Bit-Based Processing
5.2.3 Error Correction
5.3 Real-Time Requirements
5.4 Memory Issues
Bibliography
6 RelatedWork
6.1 Introduction
6.2 Rice University – Imagine
6.3 Morpho Technologies – M-rDSP
6.4 Sandbridge Technologies – Sandblaster
6.5 SystemOnIC – Hipersonic
6.6 Other Solutions
6.7 Discussion
Bibliography
III The BBP1 Architecture
7 The BBP1 Baseband Processor Architecture
7.1 Introduction
7.2 Architecture Overview
7.2.1 The Network
7.2.2 The DSP Core
7.2.3 The MAC Unit
7.3 Vector Instructions
7.4 The Accelerator Network
7.4.1 Accelerator Chaining and Function Level Pipelining
7.5 Data Memory Architecture
7.5.1 Address Generation
7.6 Function Level Acceleration for BBP1
7.6.1 Channel Coding
7.6.2 Scrambling
7.6.3 Interleaving
7.6.4 Demapping
7.6.5 Walsh Transform
7.6.6 CRC
7.6.7 Front-End Accelerator
7.7 Design Variations and Scalability Issues
7.7.1 Scalability – Increasing Computing Capacity
7.7.2 Simultaneous Multi-Standard Processing
7.7.3 The Network
Bibliography
8 Implementation
8.1 Introduction
8.2 Design Tools
8.2.1 The Assembler
8.2.2 The Instruction Set Simulator
8.3 Firmware
8.4 Prototype Chip
8.5 Test Board and Measurement Setup
Bibliography
IV Conclusions and Future Work
9 Conclusions
9.1 Issues in Design of Programmable Baseband Processors
9.2 An Architecture for Efficient Baseband Processing
9.3 Implementation Results
10 FutureWork
10.1 ISA Improvements
10.2 Architecture Scaling
10.3 Acceleration
10.4 Low-Power Features
10.5 Hardware
10.6 Firmware Design Tools
Bibliography
V Appendix
Author: Tell, Eric
Source: Linköping University
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